The Core Memory Project



NCR Century Series

NCR Century 251

The NCR Century 251, highly flexible and easily expandable, is designed for the user whose present needs require a medium-scale data processing system yet whose changingNCR Century 251 needs require that the system be flexible to handle increasing loads without extensive replacement of hardware. The capabilities of the NCR Century 251 are easily expandable through a series of optional features; by adding the "performance package" feature, it may be upgraded to an NCR Century 300 on the customer's premises. The NCR Century 251 was an enhanced 615-200 (actually it was an updated entry level 615-300).

Advanced hardware technology, using the latest in integrated circuit and memory components, the most advanced NCR Operating systems, and a set of 71 hardware commands, establishes the NCR Century 251 as a powerful base system that may be modified easily to meet the customer's growing demands on the system.

In keeping with the NCR Century philosophy of upward compatibility, programs compiled on smaller NCR Century systems may be run on the NCR Century 251, without recompilation.

System Organization

The NCR Century 251 system consists of Memory, Arithmetic Logic Processor (ALP), Input-Output Control (IOC) and common trunk facilities for a wide array of peripherals, online communication devices and three integrated peripheral units for controlling and communicating with the system. The integrated peripherals are the I/O Writer, the CRT Display Unit, and the Interval Timer.


Memory, available in six sizes 96K, l28K, 192K, 256K, 384K and 5l2K, is housed in one Memory Storage Unit (MSU) cabinet. (K = 1024 bytes) Information in memory is stored in 8-bit bytes, which may represent an 8-bit ASCII alpha or numeric character, an 8-bit binary number, or an 8-bit binary-coded-decimal (BCD) number. BCD numbers may be packed (two BCD numbers in one 8-bit byte) or unpacked (one BCD number in one 8-bit byte). When packed BCD fields are unpacked, hardware logic sets the proper zone bits to represent an ASCII character. Numeric fields may be signed or unsigned, in fixed or floating point format. Data fields are variable in length and accessible one byte at a time (byte-addressable).

For increased throughput, data putaway to and retrieval from memory is performed one word (4 bytes) at a time. A word consists of 36 bits, 32 data bits and 4 parity bits. The parity bits are transparent to the program and the external data representation. When data is stored in memory, parity bits are generated by parity logic and stored in memory with the data bits; when data is read from memory, parity bits are checked to assure the correctness of the data being read and to detect hardware malfunctions, and then discarded.

Memory Access Ports

The ALP and the IOC access the Memory Storage Unit through memory interfacing logic called ports. The ALP and the IOC have independent memory access ports, which reduces the memory contention time, and increases the effective memory access speed.

The access ports have established priorities, with the IOC using a higher priority port than the ALP. When the two units request access to the same memory module at the same time, the IOC accesses the memory module before the ALP.

The memory storage unit consists of two Memory Modules (MM), each equal to half of the total memory capacity. Each MM is capable of cycling independently.

Through the memory access ports, the IOC and the ALP have access to either MM. This makes it possible for the IOC to access one memory module while the ALP is accessing the other one, causing the MM's to cycle simultaneously, further reducing the effective access time and increasing the access speed.

The following illustration shows the internal organization of an MSU and the access ports to the MSU from the IOC and the ALP.

Memory Addressing and Address Interleaving

Memory locations are addressed binarily, by byte, from zero to the limit of the physical memory size. Data bytes are grouped into words of 4 bytes each, which are stored consecutively in alternate memory modules. Alternating the data addresses between the two memory modules minimizes the chances of the IOC or the ALP having to access the same module twice in a row. This concept of memory addressing, known as memory address interleaving, has two advantages over single-access non-interleaved memories: (1) increases the speed of data putaway or retrieval, since the processor, which requires less time to operate than memory, can cycle the other module before the first module has finished cycling, and (2) increases the throughput of the system, since the ALP and the IOC can access memory simultaneously.



 The Core Memory Project.
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